I'll try to give you a short overview over the elements and their mechanics 
The logic gates are AND, NAND (not and), OR and XOR (exclusive or) will give you based on their inputs on the side (in the following table x and y) the result (marked as r) at the top - T stands for true or a high signal F for false or a low one:
Except for the exclusive or there are no surprises as the words are used the same manner in everyday language. For XOR remember, that if both inputs are the same, the output will be false and if they are different, the result will be true.
The not element negates a signal, this means False will give you True as a result, and vice versa.
Each of the gates has a delay of 1 tick to it, this means, the output will not be instant. If you e.g. realize a diode by putting two not gates after each other, there will be a delay of two ticks compared to the reference signal.
The latch gates are a bit trickier - they are essentially what is more well known as D-latches (compared to a D-flip-flop which is edge-sensitive it is level-sensitive, sometimes called transparent D-flip-flop), this means they will change their state according to the data (D) input as long as the enable (E) input is high. You can use them to store the input state.
To get more detailed information about all the logic gates, I recommend using the internet and a search engine of your choice. If you search for the electronic real world counterparts you will find a lot of detailed explanation (much more than I or anyone else could ever write here) and examples of using them B) (Keep as well in mind, wikipedia is never the worst starting point...)
If you have any specific questions about their behavior especially their mechanics within CC2 I and I guess a lot of other members are glad to help...
The logic gates are AND, NAND (not and), OR and XOR (exclusive or) will give you based on their inputs on the side (in the following table x and y) the result (marked as r) at the top - T stands for true or a high signal F for false or a low one:
Code:
r: AND (*)
x y r
(T,T,T)
(T,F,F)
(F,T,F)
(F,F,F)
r: NAND
x y r
(T,T,F)
(T,F,T)
(F,T,T)
(F,F,T)
r: OR (+)
x y r
(T,T,T)
(T,F,T)
(F,T,T)
(F,F,F)
r: XOR
x y r
(T,T,F)
(T,F,T)
(F,T,T)
(F,F,F)Except for the exclusive or there are no surprises as the words are used the same manner in everyday language. For XOR remember, that if both inputs are the same, the output will be false and if they are different, the result will be true.
The not element negates a signal, this means False will give you True as a result, and vice versa.
Each of the gates has a delay of 1 tick to it, this means, the output will not be instant. If you e.g. realize a diode by putting two not gates after each other, there will be a delay of two ticks compared to the reference signal.
The latch gates are a bit trickier - they are essentially what is more well known as D-latches (compared to a D-flip-flop which is edge-sensitive it is level-sensitive, sometimes called transparent D-flip-flop), this means they will change their state according to the data (D) input as long as the enable (E) input is high. You can use them to store the input state.
Code:
D E Q
(F,T,F)
(T,T,T)
(x,F,Q previous)To get more detailed information about all the logic gates, I recommend using the internet and a search engine of your choice. If you search for the electronic real world counterparts you will find a lot of detailed explanation (much more than I or anyone else could ever write here) and examples of using them B) (Keep as well in mind, wikipedia is never the worst starting point...)
If you have any specific questions about their behavior especially their mechanics within CC2 I and I guess a lot of other members are glad to help...